Register-Transfer Module Selection for Sub-Micron ASIC Design

SUMMARY In order to shorten the time-to-market, Application-Specic Integrated Circuits (ASIC's) are designed from a library of pre-dened layout implementations for register-transfer modules such as multipliers, adders, RAM, ROM, etc. Current approaches to selecting the implementations from the library usually deal with their timing-area estimates and do not consider delay of the intermodule wiring. However, as sub-micron design rules are utilized for IC fabrication, wiring delay becomes comparable to the functional unit delay and can not longer be ignored even in register-transfer synthesis. In this paper we propose an algorithm that combines module selection with Performance-Driven module placement and reduces an impact of wiring on sub-micron ASIC performance. The algorithm not only eciently exploits multiple module realizations in the design library, but also nds the module placement which minimizes wiring delay. Experimental results on several benchmarks show that considering both module and wiring issues, more than 30% reduction of the total circuit delay can be achieved. 1. Introduction Module selection is one of the key tasks encountered during the synthesis of Application Specic Integrated Circuits (ASICs) at Register-Transfer Level (RTL). Given a netlist of generic resources produced by high-level synthesis, and design constraints (e.g. the minimal clock frequency, area limits), the problem is to assign a particular hardware module from the RTL design library for each of the resources. Modules are constructed by parameterized module generators and are distinguished by function, area and delay characteristics. Since, the alternative module implementations for the same resource can largely dier in the area/delay estimates, mapping decisions have a profound impact on the area and performance of the nal design. Current approaches to this problem presented in [1]-[4] usually deal with timing models of RTL components and do not consider delays in interconnections. However, in design of high-performance ASICs which are to be fabricated in a sub-micron technology, wiring delay cannot be longer ignored. An experimental mod-eling of CMOS VLSI components for dierent design rules [5] shows that delay of a wiring with an 1-mm length is becoming comparable to a 16-bit multiplier Manuscript received Manuscript revised y The authors are with the delay, as device feature sizes enter in deep sub-micron region. In design of sub-micron circuits, RTL module selection might not reach the goal of performance optimization if wiring delay is not considered. We claim that tools for register-transfer synthesis of sub-micron ASICs will not be able to make intelligent module mapping …